An embodiment of a method of forming a high density structure is known from U.S. Pat. No. 7,014,727. The known method is arranged to form a suitable pattern of an electric circuit partially in a volume of a substrate and partially on a surface of the substrate and comprises the steps of: laminating the substrate with a dielectric material in which at least some structures of the electrical circuit are to be formed; milling the substrate and the dielectric material for forming suitable cavities, filling the thus formed cavities in the substrate and in the dielectric material with an electrically conductive substance. In the known method, the dielectric layer is conceived to substantially match a surface area of the substrate. In order to remove the dielectric layer from the surface of the substrate the known method comprises supplementary steps of laminating a further layer on top of the semiconductor layer, baking the thus provided structure for enabling due adherence between the dielectric layer and the further layer. Removing the further layer together with the dielectric layer for forming an electrical circuit partially embedded in the substrate and partially arranged on a surface of the substrate, said electrical circuit being composed only of the electrically conductive material and the substrate material.
The known method has a number of disadvantages. First, it comprises a number of processing steps unnecessary complicating manufacturing process. For example, a releasable dielectric material is provided for forming structures on the surface of the substrate, which can only be removed by application of a further layer. In addition, in the known method the further layer has to be adhered to an outer surface of the dielectric layer during a baking step. As a result, residuals of the semiconductor layer may be left behind when surface adherence between the dielectric layer and the substrate is stronger than surface adherence between the dielectric layer and the further layer.